module vivada_fifo (
    input       wire            clk_50m,
    input       wire            rst_n,
    output      wire    [16:0]  sum             //输出sum，主要是为了防止练习程序信号被优化掉
);
    
    wire            empty;
    wire    [15:0]  din;
    wire            full;
    wire            wr_en;

    //写操作模块
    write_operate write_operate_inst(
        .clk_50m            (clk_50m),
        .rst_n              (rst_n),
        .empty              (empty),
        .full               (full),
        .din                (din),
        .wr_en              (wr_en)
    );   
    
    wire    [15:0]  dout;
    wire            rd_en;
    
    //读操作模块
    read_operate read_operate_inst (
        .clk_50m           (clk_50m),
        .rst_n             (rst_n),
        .empty             (empty),
        .full              (full),
        .dout              (dout),
        .rd_en             (rd_en),
        .sum               (sum)             //模拟对dout数据的处理
    );
    
    //例化FIFO核   
    wire        almost_full;
    wire        almost_empty;
    wire [9:0]  data_count;

    fifo inst_fifo (
        .clk(clk_50m),                // input wire clk
        
        .din(din),                    // input wire [15 : 0] din
        .wr_en(wr_en),                // input wire wr_en
        .full(full),                  // output wire full
        .almost_full(almost_full),    // output wire almost_full      
        
        .rd_en(rd_en),                // input wire rd_en
        .dout(dout),                  // output wire [15 : 0] dout
        .empty(empty),                // output wire empty
        .almost_empty(almost_empty),  // output wire almost_empty
        
        .data_count(data_count)       // output wire [9 : 0] data_count
    );
    
endmodule
